The present invention is related to the field of computer architecture and organization and, more particularly, to the high speed operation and synchronization of processor units operating in parallel.
A general goal for computers is faster and faster operation. One solution has been to develop individual processor units with higher operating speeds. Other solutions have been to develop computers with multiple processor units operating in parallel. Compared to a computer with a single processor, parallel computers have not had the desired increase in operating speeds as might be expected. As the number of parallel processor units have increased, parallel processing has become much more complex and the marginal increase in operating speeds with additional processor units has fallen.
Certain types of data processing are particularly suitable for parallel processors. So-called "number crunching" and graphics calculations are examples. Often processing calls for the logical merging of several calculations into a single result. For example, such logical merging from several sources could be used to create an address to a look-up table for complex functions. Several pixel values could be logically merged into a single pixel value for video image storage. The parallel processors could be performing logic simulation in which the operation of a multitude of logic AND and OR gates could be replaced by a logical merge operation.
This leads to the synchronization of operations between the parallel processors, which has been one of the impediments to high speed parallel processing. Synchronization between parallel processor units is a requirement in parallel processor computers to keep one processor from getting too far ahead (or behind) the other processor. For example, typically parallel processor units receive data processed by other units to continue processing. Synchronization forces the parallel units to stay in step with each other and not to outrun the required data.
The present invention offers a bitmerge operation by which the output data of multiple parallel processor units are synchronized and merged at high speed. Once the processor units have their data ready, the bitmerge operation is performed in a single operation.